The invention relates generally to semiconductor device fabrication and, in particular, to methods for planarizing layers of dielectric material during semiconductor device fabrication and structures formed by the planarization methods.
The manufacture of integrated circuit chips generally involves the deposition and patterning of a series of layers composed of different types of materials. In the semiconductor industry, chemical mechanical polishing (CMP) is a commonly used technique for smoothing, planarizing, and/or removing layers from a wafer during manufacture. To execute a CMP process, a wet abrasive and corrosive slurry is dispersed between the surface to be polished and a flexible polishing pad. The polishing pad has a contacting relationship with the surface and the polishing pad and wafer are spun relative to the other to smooth and planarize (i.e., flatten) the contacted surface on the wafer by material removal. The CMP system typically includes a polishing head that presses the rotating wafer against the flexible polishing pad. The CMP process combines the chemical removal effect of an acidic or basic fluid solution operating as the carrier of the slurry with the mechanical removal effect provided by an abrasive material of the slurry that is suspended in the carrier.
Improved methods and structures are needed for CMP processes, especially CMP processes employed to planarize material layers used in semiconductor device fabrication and, in particular, CMP processes employed to planarize interlayer dielectric layers used in fabricating back-end-of-line (BEOL) interconnect structures.